LVDS on i.MX6

The FSL IPU is Image Processing Unit, a part of video and graphics subsystem in an application processor. The goal of the IPU is to provide comprehensive support for the flow of data from an image sensor or/and to a display device.

Two IPU units are on the iMX6Q SOC while only One IPU unit on the iMX6DL SOC.

Each IPU has two display ports which can be configured to send the image data either to the parallel RGB port or to the serializer bridges (HDMI, MIPI or LVDS).

The LVDS Display Bridge (LDB) is used to coect the IPU to external LVDS displays (LVDS0 and LVDS1). With the two available LVDS chaels the following configurations are supported:

· Single Mode: only one LVDS chael is used (LVDS0 or LVDS1)

· Dual Mode: one image stream is duplicated to both chaels (LVDS0 = LVDS1)

· Separate Mode: LVDS0 and LVDS1 are used to output different image streams. That’s the default setting to support multiple displays with different contents.

· Split Mode: one image stream is split to both LVDS chaels to get a high bandwidth for high resolution displays.

=> setenv bootargs_mmc 'setenv bootargs ${bootargs} root=/dev/mmcblk1p1 rootwait rw video=mxcfb0:dev=ldb,LDB-XGA,if=RGB24'

=> saveenv

=> reset