GS8320Z18/36T - 36Mbit Synchronous Static SRAM

entity gs8320z36gt_sram_ctrl is

generic

(

sram_hold_time : time := 500 ps;

read_after_write : integer := 0;

data_width : integer := 36;

addr_width : integer := 20

);

port

(

clk : in std_logic;

rst : in std_logic;

sram_addr : in std_logic_vector(addr_width-1 downto 0);

sram_rd_en : in std_logic;

sram_wr_en : in std_logic;

sram_din : in std_logic_vector(data_width - 1 downto 0);

sram_dout : out std_logic_vector(data_width - 1 downto 0);

sram_rd_ack : out std_logic;

sram_wr_ack : out std_logic;

SRAM_DQ : inout std_logic_vector(data_width - 1 downto 0);

SRAM_A : out std_logic_vector(addr_width - 1 downto 0);

SRAM_CLK : out std_logic;

SRAM_CLKEL : out std_logic;

SRAM_WL : out std_logic;

SRAM_GL : out std_logic;

SRAM_E1L : out std_logic;

SRAM_BAL : out std_logic;

SRAM_BBL : out std_logic;

SRAM_ADV : out std_logic;

SRAM_ZZ : out std_logic;

SRAM_FTL : out std_logic;

SRAM_LBOL : out std_logic

);

end entity;

...

signal io_direction : std_logic; -- output = '0' / input = '1'

...

IOBUF1_for:

for i in 0 to data_width - 1 generate

IOBUF_Inst: IOBUF

port map

(

O => sram_dout(i),

IO => SRAM_DQ(i),

I => sram_din_r3(i),

T => io_direction

);

end generate;